FIELD: computer engineering. SUBSTANCE: device has two registers, two adders, D-flip-flop, OR gate, two multiplexers, unitary code generation unit, shift unit, unit for storage of constants. EFFECT: increased speed due to multiplicative algorithm of half-argument processing. 2 dwg
| Title | Year | Author | Number | 
|---|---|---|---|
| DEVICE FOR REDUCING FUNCTION TO MULTIPLICATION ALGORITHM | 1990 | 
 | RU2028659C1 | 
| DEVICE FOR CALCULATING NATURAL LOG OF COMPLEX NUMBER | 1991 | 
 | RU2010312C1 | 
| DEVICE FOR MULTIPLICATION OF INTEGERS WITH S-BIT LENGTH IN POSITION-REMAINDER NUMBER SYSTEM | 1991 | 
 | RU2006919C1 | 
| DEVICE FOR CALCULATING FUNCTIONS | 0 | 
 | SU1705822A1 | 
| DEVICE FOR COMPUTING FUNCTIONS | 1988 | 
 | SU1755650A1 | 
| 0 |  | SU448459A1 | |
| A-D CONVERTER | 0 | 
 | SU1612374A1 | 
| DEVICE FOR CALCULATING VALUE OF SQUARE ROOT OF NUMBER IN MODULAR NUMBER SYSTEM | 0 | 
 | SU1317434A1 | 
| DIVIDER | 0 | 
 | SU1742815A1 | 
| COMPLEX SIGNAL CONVERTER | 0 | 
 | SU1104525A1 | 
Authors
Dates
1994-01-30—Published
1991-07-25—Filed