FIELD: electric communication. SUBSTANCE: device has unit 1, 2 for separating an input train of multi-level pulses into two synchronous even and odd pulse subtrains with regard to occurrence order of the pulses; units 3, 4 for delaying the pulses by 16 clock periods, integrators 5, 6 for computing separately a sum of two trains of 16 even and odd pulses for 16 clock periods of each train, main integrators 10, 11 for computing separately a total code sum of even and odd pulses, the main integrators being adapted for operating both in an add mode and in subtract one. If the sums stored in integrators 5, 10 and 6, 11 coincide in sense, the subtrains are inverted in units 13, 14 and the main integrators operate in a subtract mode. If the sums stored in integrators 5, 10 and 6, 11 differ in sense, inversion in units 13, 14 doesn't occur and main integrators 10, 11 operate in add mode. The device furthermore has unit 20 for producing a cycle pulse for transmitting information on inversion or non-inversion of the predetermined group of 32 pulses, unit 21 for combining the even and odd pulse subtrains with the cycle pulse, in even groups pulses occurring in natural order and in odd ones even and odd pulses being interchanged with the aid of switches 17, 18, delay elements 15, 16 and shaper 19; control unit 22 for synchronizing and controlling the operation of code units. EFFECT: enhanced accuracy of balancing d c component and reduced power of half-clock frequency signal. 1 dwg
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Authors
Dates
1994-06-30—Published
1990-12-10—Filed