FIELD: computer technology. SUBSTANCE: k(k=1,2,3...) m-digit address registers are introduced into the device. Information is recorded into the registers in sequence. Device also has corresponding functional couplings. Increase in capacitance is achieved, connected with memory processor in 2mk times. Device has control unit, address register, receivers-transmitters, decoder and groups of OR gates. EFFECT: improved capacitance. 1 tbl, 3 dwg
Title | Year | Author | Number |
---|---|---|---|
DEVICE FOR INTERFACING PROCESSOR WITH MEMORY | 0 |
|
SU1345203A1 |
PROCESS CONTROL COMPUTER SYSTEM | 0 |
|
SU1451711A1 |
COMPUTING SYSTEM | 0 |
|
SU1734101A1 |
DEVICE FOR INTERFACE BETWEEN UPPER LEVEL PROCESSOR AND LOWER LEVEL PROCESSOR GROUP IN HIERARCHICAL MULTIPROCESSOR SYSTEM | 0 |
|
SU1789988A1 |
DEVICE FOR CONNECTING TWO MAIN LINE | 0 |
|
SU1675894A1 |
PROCESSOR/MEMORY INTERFACE | 0 |
|
SU1481779A1 |
STORAGE | 0 |
|
SU1251175A1 |
DEVICE FOR INTERFACING COMPUTER BUS WITH PERIPHERALS | 0 |
|
SU1751775A1 |
0 |
|
SU1564626A1 | |
DYNAMIC DIRECT-ACCESS STORAGE | 0 |
|
SU1499401A1 |
Authors
Dates
1994-08-30—Published
1991-07-09—Filed