FIELD: computer engineering. SUBSTANCE: device having sequential approximation register, two-matrix code-to-voltage converter, selector switches, two comparators, OR gate, pulse generator, positive reference-voltage generator, delay element, AND gate, first flip flop is provided in addition with second and third flip-flops, two NOT gates, second OR gate, six AND gates, second delay element, resistive divider, four reference-voltage sources, electronic switch. Measured voltage-to-code conversion is effected in reduced conversion cycle. END-OF-CONVERSION signal is shaped at the moment when difference between measured and compensating voltages becomes lower than less significant bit value. Sequential approximation register shapes m-bit code. When difference between measured and compensated voltages at the last conversion step is higher than less significant bit value, compensating voltages of Ucomp ± Ulsb are generated at check step. When difference between measured and compensated voltages is lower than double value of less significant bit, m-1 bit code is generated in sequential approximation register, otherwise failure signal is shaped. To compensate for error appearing in enabling more significant bit, (m+1) resistors 2R of R-2R resistive matrices in device are connected through switch and voltage divider to positive reference-voltage source. EFFECT: improved validity and speed of check, higher reliability of device. 1 dwg
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INVERTED D-A CONVERTER WITH R-2R RESISTOR MATRIX | 0 |
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SU959273A1 |
Authors
Dates
1994-09-30—Published
1991-06-26—Filed