FIELD: computer engineering. SUBSTANCE: known device having first address counter 6, second address counter 10, and third address counter 11 whose address inputs are connected to outputs of reference generator 7 and outputs of first and second address counters are connected, respectively, to first and second address inputs of first read-only storage unit 8, and also input register 3 whose data input functions as digital filter input, output of device being output of output register 2, is provided in addition with second read-only storage unit 9, main storage 4, and multiplying accumulator 1, all inserted between output of third address counter 11 and data input of output register 2, as well as ratio storage unit 5 connected between output of third address counter and data input of multiplying accumulator 1, its other address input being combined with other address input of second read-only storage unit 9 and with first address input of first read-only storage unit 8 whose control output is connected with control inputs of main storage, input and output registers, and multiplying accumulator and its address input is connected to other address input of main storage; output of multiplying accumulator 1 is combined with output of input register 3 and with main storage input/output. EFFECT: improved speed. 1 dwg
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Authors
Dates
1994-11-30—Published
1990-07-02—Filed