FIELD: storage devices. SUBSTANCE: device has accumulator 1, check register 2, error signal shaper 3, adder 4, first and second OR gates, AND gate 7, first 8, second 9, third 10, fourth 11, fifth 12 delay elements, first 13, second 14, third 15 registers, first 16, second 17, third 18, fourth 19 groups of AND gates, first 20 and second 21 groups of OR gates. EFFECT: enhanced reliability and widened application range. 2 dwg
Title | Year | Author | Number |
---|---|---|---|
DEVICE FOR PROCESSOR-MEMORY INTERFACE | 0 |
|
SU1059560A1 |
REDUNDANCY STORAGE | 0 |
|
SU1437917A1 |
STORAGE WITH SELF-CHECK | 0 |
|
SU1188784A1 |
ON-LINE MEMORY DEVICE HAVING FAULTY CELL BLOCKING | 0 |
|
SU1014033A1 |
STORAGE WITH SELF-CHECKING | 0 |
|
SU1249592A1 |
TWO-LEVEL ON-LINE STORAGE | 0 |
|
SU1043742A1 |
STORAGE WITH SELF-CHECK | 0 |
|
SU1094071A1 |
DEVICE FOR CHECKING READ-ONLY MEMORY BLOCKS | 0 |
|
SU1125657A1 |
DEVICE FOR CORRECTING ERRORS IN MEMORY BLOCKS | 0 |
|
SU1257708A1 |
PRIMARY STORAGE | 0 |
|
SU1095233A1 |
Authors
Dates
1994-12-15—Published
1990-10-09—Filed