FIELD: computer engineering. SUBSTANCE: device has m registers p1...pm, 2m-1 adders subtracters S1...S2m-1 m sign decoders, two shifters 1, 4, unit 1 of change of sign of number 2 and multiplier 3 by one of n constants, m inputs x1...xm of operands, m inputs Z1...Zm for analysis of sign of operand, m outputs of result y1...ym and input 5 of iteration number. As distinct from known technical approaches proposed device conducts conversion of components of vector in m-dimensional space as one macrooperation for time of order of duration of n addition operations. Besides this result of operation does not deform (elongation factor of vector equals one). Efficiency is achieved expansion of functional capabilities of device due to m-dimensional Householder's conversion with relatively insufficient additional use of components of equipment. EFFECT: expanded functional capabilities of device. 3 dwg
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Authors
Dates
1995-02-20—Published
1992-01-22—Filed