FIELD: electronic circuits. SUBSTANCE: code converter has second flip-flop connected through its J,K, and C inputs, respectively, to output, first NOT gate input, and fourth NOT gate output connected to C inputs of fourth, fifth, sixth, and seventh flip-flops and to C input of third flip-flop whose K input is connected to inverter output of NAND gate connected via third NOT gate to J input of third flip-flop which is connected through its direct output to J input of fourth flip-flop and to third input of second NAND gate whose inverted output is connected to K input of fourth flip-flop connected through its direct output to J input of fifth flip-flop and to second input of second NAND gate and through its inverted output, to K input of fifth flip-flop whose output is connected to second input of fourth NAND gate whose inverted output is connected to J input of sixth flip-flop and to input of sixth NOT gate whose output is connected to K input of sixth flip-flop. EFFECT: reduced error in code conversion. 1 dwg
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Authors
Dates
1995-02-20—Published
1990-08-07—Filed