FIELD: computer engineering. SUBSTANCE: device is provided in addition with fourth AND gate whose first input is coupled with output of second delay element and second one, with forward output of data retrieval flip-flop, and its output is connected to data entry output of second buffer register and flip-flops, two buffer registers, adder, setting register, comparison circuit, four AND gates, two delay lines, inverter, data retrieval flip-flop, two ready buses, data retrieval bus. EFFECT: improved reliability of device due to making it impossible to change state of second buffer register during its output data reading. 1 dwg
Title | Year | Author | Number |
---|---|---|---|
DATA SOURCE-PROCESSOR INTERFACE | 0 |
|
SU1767501A1 |
DATA SOURCE-TO-PROCESSOR INTERFACE | 1991 |
|
RU2024051C1 |
DATA-SOURCE-TO-PROCESSOR INTERFACE | 0 |
|
SU1774341A1 |
DEVICE FOR INTERFACING INFORMATION SOURCE TO PROCESSOR | 0 |
|
SU1658165A1 |
DEVICE FOR INTERFACING INFORMATION SOURCE AND PROCESSOR | 0 |
|
SU1571601A1 |
DEVICE FOR INTERFACING INFORMATION SOURCE TO PROCESSOR | 0 |
|
SU1658162A2 |
DEVICE FOR INTERFACING INFORMATION SOURCE WITH PROCESSOR | 0 |
|
SU1689960A2 |
DEVICE FOR INTERFACING INFORMATION SOURCE WITH PROCESSOR | 0 |
|
SU1686451A1 |
DEVICE FOR INTERFACING INFORMATION SOURCE WITH PROCESSOR | 0 |
|
SU1689958A2 |
PROCESSOR FOR MULTIPROCESSOR SYSTEM | 0 |
|
SU1295410A1 |
Authors
Dates
1995-04-20—Published
1991-05-30—Filed