FIELD: computer engineering. SUBSTANCE: device has l computing units, P parallel registers, where to P = (n+1)*(n+m) - l*(n+3) and m is number of columns in right-hand part of the system of linear algebraic equations. In addition device has two shift registers having P-bit length, unit of OR gates and two OR gates. Each computing unit has three registers, gate for n-pulse delay, two flip-flops, two groups of flip-flops, multiplier, unit for computing inverse fraction value, subtracter, nine groups of AND gates, four groups of OR gates, five AND gates and two NOT gates. Proposed device solves system having n algebraic equations by means of fixed number of L computing units when l<n. EFFECT: decreased hardware. 2 dwg
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Authors
Dates
1995-06-09—Published
1990-05-23—Filed