TWO STAGE DEVICE FOR CORRECTING ERRORS Russian patent published in 1995 - IPC

FIELD: computer engineering. SUBSTANCE: device has two stages of error correction, each having a register unit, a modulo two convolution unit of oblique parity, two "Non-equivalence" gates, a unit for error detection by analyzing the number of bits on each level, a multiple error detection unit, shift register, AND gate group, modulo two adder unit, shift register, AND gate group, modulo two adder unit, NOT gate, output bus. The second stage of error correction has stepwise shift register with shift increasing when moving from the Nth bit to the first bit, with the step being equal to m. The device corrects single errors at the first level using the second vertical and oblique parity. The first vertical and oblique parities are taken as N+1 and N+2 information bits and error batches of the length m-1 which are transformed by stepwise shift register at the second level. Single stepwise shifted errors are corrected by using coupled oblique and vertical parities increasing reliability of read data. EFFECT: enhanced reliability in reading data, higher density in information storage. 6 dwg