REDUNDANT COMPUTER SYSTEM Russian patent published in 1995 - IPC

FIELD: computer engineering. SUBSTANCE: device has three computing units 1, 2, 3, three output units 4, 5, 6, two memory units 7, 8, three input units 9, 10, 11, commutator 12, register 13, two OR gates 14, 15, flip-flop 16, two AND gates 17, 18, two delay gates 19, 20. Each computing unit has testing unit 21 having multichannel signature analyzer 22, first and second flip-flops 23, 24, AND gate 25. This unit provides testing operations of pairs of computing units in each testing cycle. Testing cycle corresponds to time of computation each software module in computing unit. Same software modules are assigned for execution to each mutually tested computing units. Test in each testing cycle is provided by generation of two signatures for each pair of computing units. Result of addition of these signatures by modulo two should be equal to zero if pair of computing units operates correctly. If fault happens, this result equals to one. EFFECT: generation and comparison of instruction flow signatures for pair of tested computing units. 2 cl, 6 dwg, 1 tbl