PARALLEL ADDER OF FIBONACCI CODES Russian patent published in 1995 - IPC

FIELD: computer engineering. SUBSTANCE: device has read-only memory units 1-4, input registers 8.1, 8.N, control register 6, control flip-flop 7, delay unit 5.1, delay gates 5.2-5.P, OR gates 9.1-9.K1, 12.1-12.K2, 13, 18.1, 18.2, AND gates 10.1-10.N, 11.1-11.K2, 16, 17.1-17.K2, 19.1- 19.3, NOT gates 14,20, triple-input NOR gate 15, synchronization inputs 1, information inputs 2, information outputs 1-/n+m/. Device provides possibility of simultaneous addition of N n-bit integers which are represented in arbitrary form of Fibonacci number system. EFFECT: increased speed. 1 dwg