FIELD: computer engineering, TV devices. SUBSTANCE: registers for 21 and 22 for change of scale rates by line and column respectively, four registers 23-26 for storing boundary of fragment, two dividers 27 and 28, registers 36 and 35 for storage of reading step in columns and lines respectively, six subtracters 29-34, two halving dividers 37-38, four multipliers 39-42 and eight adders are introduced to accomplish the goal of invention. Device may be used for generation of complex TV picture which contains background where controlled fragment is inserted and may be change in size. Device implements algorithm which scales only for two points of boundary. Then, run-time address of each element for decomposition is generated as sum of address of background elements to that of reading step. EFFECT: increased speed. 1 dwg
Title | Year | Author | Number |
---|---|---|---|
TV PICTURE DRIVER WITH CONTROLLED DISPLACEABLE FRAGMENT | 0 |
|
SU1644171A1 |
DEVICE FOR ORTHOGONAL CONVERTING DIGITAL SIGNALS | 1989 |
|
RU2012047C1 |
IMAGE READER | 1992 |
|
RU2045781C1 |
0 |
|
SU1783581A1 | |
INTERFACE FOR LINKING COMPUTER WITH IMAGE INPUT DEVICE | 0 |
|
SU1260967A1 |
BUFFER STORAGE | 0 |
|
SU1280457A1 |
DEVICE FOR ACCELERATED CALCULATING MATRIX OF INCOMPLETE PARALLELISM | 2016 |
|
RU2634200C1 |
DEVICE FOR SOLVING EQUATIONS OF MATHEMATICAL PHYSICS | 0 |
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SU1363260A1 |
DEVICE FOR INTERPOLATION OF TV PICTURE SIGNAL | 0 |
|
SU1690213A1 |
0 |
|
SU1783635A1 |
Authors
Dates
1996-08-10—Published
1993-07-08—Filed