FIELD: computer engineering, instruments. SUBSTANCE: first claim of invention describes device design which has voltage rectifier 1, analog-to-digital converter 2, digital comparator 3, delay gates 4 and 5, NAND gates 6-8, 14, 22 and 23, flip-flops 9, 18, 19, 27-32, reverse counter 10, clock oscillator 11, control counter 12, univibrators 13, 15, 16, 20, 21, 25, binary counter 17, NOT gates 24, 26, 62, decoders 33-38, which translate binary code to seven-digit code, setters 39-44, which provide binary code for digits 0 to 5, seven-digit indicators 45-50, resistor 51, control button 52, decoder 53, which translates binary code to unitary position code, pulse counters 54-61. Another claim of invention describes device design which has voltage rectifier 1, analog-to-digital converter 2, digital comparator 3, delay gates 4 and 5, NAND gates 6-8, 14, 22 and 23, flip-flops 9, 18, 19, 27-32, reverse counter 10, clock oscillator 11, control counter 12, univibrators 13, 15, 16, 20, 21, 25, binary counter 17, NOT gates 24, 26, 62, decoders 33-38, which translate binary code to seven-digit code, setters 39-44, which provide binary code for digits 0 to 5, seven-digit indicators 45-50, resistor 51, control button 52, decoder 53, which translates binary code to unitary position code, memory unit 64, level distributor 65, binary-decimal counter 66. This results in possibility to remove pulse race at outputs of digital comparator during transient processes when digit codes are changed at its inputs. EFFECT: increased functional capabilities, facilitated use due to parallel statistic analysis and continuous visual monitoring of current voltage oscillation range, increased reliability and validity. 2 cl, 4 dwg
