FIELD: computer engineering, in particular, file verification, hardware tests. SUBSTANCE: device has group 2 of information inputs, clock input 3, N n-bit registers 5, where n is number of information inputs, N is power of generatrix polynomial F(x) = XN+XK+1. In addition device has two adders 4, two inputs 1.1 and 1.2 and two outputs 6.1 and 6.2 for bit-length increment. EFFECT: possibility to increase bit- length. 4 dwg, 4 tbl
Title | Year | Author | Number |
---|---|---|---|
MULTICHANNEL SIGNATURE ANALYZER | 1998 |
|
RU2133057C1 |
MULTICHANNEL SIGNATURE ANALYZER | 1996 |
|
RU2120136C1 |
STORAGE WITH INFORMATION CHECKING | 0 |
|
SU1288758A1 |
SIGNATURE ANALYZER | 0 |
|
SU1524054A1 |
MULTICHANNEL SIGNATURE ANALYSER | 0 |
|
SU1185338A1 |
SIGNATURE ANALYZER | 0 |
|
SU1264180A1 |
DEVICE FOR CHECKING BINARY SEQUENCES | 0 |
|
SU1116431A1 |
DEVICE FOR CHECKING BINARY SEQUENCE | 0 |
|
SU1128259A1 |
ANALYZER OF SIGNATURES OF PARALLEL DATA FLOW | 0 |
|
SU1403065A1 |
MONITORING CODE FORMING DEVICE | 0 |
|
SU1352489A1 |
Authors
Dates
1997-08-10—Published
1995-04-13—Filed