FIELD: computer engineering, in particular, distributed information-processing systems, information exchange between mainframe computer and remote systems through common line. SUBSTANCE: device has N channels each of which has NOR gate, AND gate, two OR gates, two NOT gates. All channels except last one also have NAND gate, flip-flop and delay gate. In addition device has access time control units, each of which has AND gate, OR gate, counter. All access time control units except last one also have OR gate. In addition device has four OR gates, two flip-flops, two delay gates, AND gate, AND gate with one inverting input, clock oscillator, unit which checks request frequency and has three counters, delay gate, NOR gate, two delay flip-flops, NOT gate, decoder, two frequency dividers and AND gate. Device provides possibility of automatic alternation of request processing mode as well automatic alternation of request pulse rate in moments which are determined by devices depending on intensity of request pulse flow which is sent to information input of any channel. EFFECT: increased functional capabilities, increased efficiency of operations. 1 tbl, 2 dwg
Title | Year | Author | Number |
---|---|---|---|
ADAPTIVE CONTROL SYSTEM | 1995 |
|
RU2093881C1 |
INTERFACE FOR LINKING PROCESSORS IN MULTIPROCESSOR SYSTEM | 0 |
|
SU1188747A1 |
MULTICHANNEL PRIORITY DEVICE | 0 |
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DEVICE FOR SIMULATING THE QUEUEING SYSTEMS | 0 |
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SU1319043A1 |
MULTICHANNEL PRIORITIZER | 0 |
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SU1661765A1 |
DEVICE FOR READING GRAPHIC INFORMATION | 0 |
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SU1244684A1 |
DEVICE FOR MODELLING DATA COLLECTION SYSTEM | 0 |
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DEVICE FOR SIMULATING QUEUEING SYSTEMS | 0 |
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MULTICHANNEL DEVICE FOR USER CONNECTION TO COMMON BUS | 0 |
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DEVICE FOR TESTING PARAMETERS | 2000 |
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RU2160919C1 |
Authors
Dates
1997-10-20—Published
1995-06-27—Filed