ADJUSTABLE DIGITAL DELAY LINE Russian patent published in 1998 - IPC

FIELD: pulse engineering; radars, radio navigation, telemetering, pulse radio communications, measurement technology, and compute engineering. SUBSTANCE: delay line has clock generator, variable-ratio frequency divider, input, output, and code buses; newly introduced in delay line is random-access memory; in addition, clock generator is provided with second output connected to resolution input of random- access memory whose write/read input is connected to first output of clock generator and to clock input of variable-ratio frequency divider whose data inputs are connected bit-by-bit to code buses while output of each bit of this frequency divider is connected to respective address input of random-access memory whose data input is connected to input bus and output, to output bus. EFFECT: improved resolving power and simplified design of line. 1 dwg