FIELD: computer engineering, in particular, digital signal processing. SUBSTANCE: device has five registers 10-12, 17, 18, two commutators 13, 14. Goal of invention is achieved by two introduced accumulating multipliers 15, 16. EFFECT: simplified design due to use of scalar multiplication algorithm with regular structure, increased speed due to simplified and regular control of computing fast Fourier transform or fast Hartley transform. 2 dwg
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