FIELD: pulse engineering; automation and computer engineering, measurement technology.
SUBSTANCE: device has optimized quantity of NAND gates 1 - 7, input bus 8, output buses 9, 10, 11, clock pulse bus 12, and capacitor 13. Newly introduced NAND gates 6 and 7 provide for eliminating time limits for synchronized pulse trains and NAND gates 4, 5 enable shaping of complete synchronous clock pulses.
EFFECT: enhanced reliability, enlarged functional capabilities.
1 cl, 2 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| DEVICE FOR SYNCHRONIZING PULSES | 0 |
|
SU1228244A1 |
| PULSER | 0 |
|
SU1465935A2 |
| PULSE GENERATOR | 0 |
|
SU1372604A1 |
| DEVICE FOR COMPARING TWO VOLTAGES | 0 |
|
SU1226636A1 |
| UNIT CODE SHIFT REGISTER | 0 |
|
SU1298805A2 |
| DEVICE FOR CLOCK SYNCHRONIZATION AND SEPARATION OF PULSE BURST | 0 |
|
SU1723658A2 |
| NON-BINARY SYNCHRONOUS COUNTER | 0 |
|
SU1742994A1 |
| DEVICE FOR COMPARING FREQUENCIES BY A STANDARD | 0 |
|
SU1659894A1 |
| BINARY CODE-TO-TIME INTERVAL CONVERTER | 0 |
|
SU1115223A1 |
| COUNTER | 0 |
|
SU1506546A1 |
