FIELD: computers.
SUBSTANCE: module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output.
EFFECT: simplified adjustment.
2 dwg
Title | Year | Author | Number |
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LOGICAL CALCULATOR | 2004 |
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RU2262734C1 |
LOGICAL COMPUTER | 2002 |
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RU2248036C1 |
LOGIC COMPUTING DEVICE | 2006 |
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RU2324219C1 |
LOGICAL CALCULATOR | 2011 |
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LOGICAL CALCULATION UNIT | 2005 |
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LOGICAL COMPUTING DEVICE | 2005 |
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Authors
Dates
2005-03-10—Published
2003-05-27—Filed