DIGITAL-TO-ANALOGUE CONVERTER Russian patent published in 2011 - IPC H03M1/66 

FIELD: electricity.

SUBSTANCE: digital-to-analogue converter comprises a master pulse generator (4), weight resistors (2_1-8), a reference-voltage source (1) with its output connected with first leads of the first and second weight resistors, a filtering operational amplifier (3₂) with a resistor and a capacitor (9) parallel connected to its feedback circuit, and with its output being an output bus of the digital-to-analogue converter, two pulse counters (6, 7), an AND component (5) with one of its inputs connected to an output of the master generator and its output connected to a countdown input of the first counter, a code unit (13), an initial start assembly (14), three slave keys (15, 16_1-2), a RS-trigger (8). There are introduced an OR component (11), a delay component (12), an amplitude modulator formed by an operational amplifier (3₁), a second capacitor (10), an adder mixer on three weight resistors (2_4-6) with its first input connected through the first slave key to the output of a reference-voltage source, the second input - to an output of the operational amplifier (3₁), while the output is connected through the second slave key to a direct input of the operational amplifier (3₂) and with a first lead of the second capacitor with its second lead connected to a common bus of the adder mixer and with a first lead of an additional resistor with its second lead connected to an inverting input of the operational amplifier (3₂); a driving input of the first slave key is connected to a direct output of the RS-trigger and to the second input of the AND component with its output additionally connected to a driving input of the second slave key, and the first input is additionally connected to an addition input of the second counter and with a control input of the third slave key working in switching with its break-make contact connected to the direct input of the operational amplifier (3₁), a first fixed contact - with the common bus, and a second one - with the second lead of the second weight resistor, while the inverse input of the operational amplifier (3₁) is connected to the second lead of the first weight resistor and through the third weight resistor with the output of the operational amplifier (3₁); the S input of the RS-trigger is connected to the output of the OR component and to the input of the delay component with its output connected to a parallel data record input from the code unit in the first counter, with its nulling R input connected to the R input of the second counter, with an output of the initial start assembly and with the first input of the OR component with its second input is connected to an overflow output of the second counter, and the output "<0" of the first counter is connected to the nulling input of the RS-trigger; the counters have equal digit capacities.

EFFECT: improved linearity of a transformation characteristic.

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