METHOD OF FACILITATING MULTIPLICATION OF TWO NUMBERS IN MODULAR-POSITION PRESENTATION FORMAT WITH FLOATING POINT ON UNIVERSAL MULTI-CORE PROCESSORS Russian patent published in 2014 - IPC G06F7/72 

Abstract RU 2509345 C1

FIELD: information technology.

SUBSTANCE: method is realised on a universal multi-core computer, having g k-bit cores, each facilitating a system of f operations which include algebraic multiplication and algebraic addition of numbers presented in position integer data formats. When facilitating multiplication operations, each number, multiplier and multiplicand, is presented in a modular-position format with a floating point in form of a (1+k+q·n)-element vector.

EFFECT: high rate of computation by replacing the operation of multiplying t-bit position mantissas of multiplicands with n concurrently executed operations of multiplying q-bit character positions of numbers in a residue number system.

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RU 2 509 345 C1

Authors

Knjaz'Kov Vladimir Sergeevich

Isupov Konstantin Sergeevich

Dates

2014-03-10Published

2012-07-27Filed