FIELD: physics.
SUBSTANCE: device comprises: the first 1ij and the second 2ij (i=1, …, n; j=1, …, k) group of registers, the third group of registers 3j(j=1, …, k), the fourth register 4, the fifth register 5, the first 6ij and the second 7ij (i=1, …, n; j=1, …, k) group of taking the logarithm, the sixth 8ij and the seventh 9ij (i=1, …, n; j=1, …, k) group of registers, the eighth register 10, a group of the first 11i and the second 15i (i=1, …, n) adder, the first 12ij, the second 13ij and the third 14ij (i=1, …, n; j=1, …, k) group of multipliers, the third adder 16, a group of the first 17i and the second 18i (i=1, …, n) division units, the third 19 and the fourth 20 division units, the fourth 21j (i=1, …, n) adders, a group of the fifth 22i (i=1, …, n) division units, the ninth register 23, a group of the tenth 24i (i=1, …, n) registers, the fifth adder 25, the sixth division unit 26, a group of the fourth 27i (i=1, …, n) multiplication units, the sixth adder 28, a group 29i (i=1, …, n) of the subtraction units, the seventh adder 30, the seventh division unit 31, the eleventh 32, the twelfth 33 and the thirteenth 34 registers, the first 35 delay element (DE), the second DE 36, the third DE 37,the fourth DE 38, the fifth DE 39, the sixth DE 40, the seventh DE 41, the eighth DE 42, the ninth DE 43, device outputs 44, 45, 46, 47, 48, 49, an entry 50.
EFFECT: increasing reliability and performance by reducing the hardware.
1 dwg
