FIELD: physics.
SUBSTANCE: proposed multiplier by module realizes this method by performing n operations, where n is the bit depth of the module. During the i-th operation, the value of z=x⋅y (where x and y are the values of the input numbers) is compared with the value 2(n-i)⋅p by calculating the difference z-2(n-i)⋅p, where i=1, …, n. The result of multiplying the number x by the number y by module p is the value of the difference obtained as a result of the n-th operation. The value 2(n-i)⋅p is calculated by sequential multiplying the module value by 2 by shifting the code of the module p to one higher by one bit. Thus, it is possible to exclude multipliers by a constant from the circuit. The range of input values for a given multiplier is determined by the size of the multiplier and is within [0, …, (p-1)].
EFFECT: reducing the amount of the used multiplier hardware by module eliminating all even multipliers by a constant from the circuit, and parts of the inverters.
1 dwg
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Authors
Dates
2017-09-07—Published
2016-11-28—Filed