FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering. Method for testing a RAM in which, by using a P-bit pseudo-random number generator based on a cyclic shift register with linear feedback and a repetition period M, whose structure is preliminarily determined based on an inequalities system, at least K test cycles are performed consecutively, each of which performs, with sequential alternation, the procedure of writing test L-bit pseudo-random numbers to all N cells of the RAM, and then the procedure for reading from each RAM cell the data recorded in them and comparing them with test pseudo-random numbers, while in the procedure for generating test L-bit pseudo-random numbers, the value of each bit in them is simultaneously formed directly or by 2-modulus convolution from the current values of bits of the P-bit pseudo-random number generator such that in each i-th bit of the j-th test word the r-th symbol of the pseudo-random sequence with the repetition period M is formed.
EFFECT: technical result consists in increasing the efficiency of detecting faults caused by the information interaction of memory elements.
1 cl, 3 dwg
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|
RU2455712C2 |
DEVICE FOR GENERATING TESTS | 0 |
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RU2234191C2 |
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SU1444781A1 |
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SU962931A1 |
TEST GENERATOR | 0 |
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SU1424020A1 |
DEVICE FOR CHECKING PRIMARY STORAGE | 0 |
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SU1091227A1 |
0 |
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SU468231A1 | |
DEVICE FOR SHAPING TESTS | 0 |
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SU1543408A1 |
Authors
Dates
2018-07-06—Published
2017-02-20—Filed