FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering. Information processing apparatus comprises a circuit configured to: obtaining the bit rate of the transmitted data; comparing the bit rate with a threshold; selecting a forward error correction coding system based on comparing the bit rate with the threshold value; transferring the transmitted data to the receiving processing device; changes in the transmission rate of the transmitted bits during the transmission of the transmitted data; comparing the changed bit rate with the specified threshold value; and altering the forward error correction coding system based on the comparison of the changed bit rate with the threshold value.
EFFECT: improved FEC-related technology for low latency transmission.
10 cl, 27 dwg
