FIELD: computer equipment.
SUBSTANCE: device contains two registers, the first of which is connected to the output of the second reversible counter, and the output is connected to the binary multiplier code input, the second register input is connected to the output of the first reversible counter, the output of this register is the code output of the pulse-width converter and simultaneously connected to the code input of the fourth logical multiplication block, and the clocking of both registers is performed by connecting the corresponding inputs with the input pulse-width signal.
EFFECT: technical result is to improve the accuracy of the pulse-width converter.
1 cl, 2 dwg
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Authors
Dates
2019-03-26—Published
2018-05-28—Filed