FIELD: digital signal processing.
SUBSTANCE: reconfigurable fast Fourier transform computer of super-long transform length for input samples comprises two "butterfly" computing units, four FIFO buffers and DMA memory direct access controller, which is connected to system bus and Control Bus control bus. At that, DMA zero channel data output Rdata0 is connected to the coefficients of the RfifoCoef coefficients buffer coefficients data input, the high-end part Coef1 of the output bus of which is connected to the input of the multiplier of the first "butterfly" unit BFly1, and the lower part Coef0 of the output bus is connected to the input of the multiplier of the zero node "butterfly" BFly0.
EFFECT: creation of a reconfigurable fast Fourier transform (FFT) computer of super-long conversion length with conflict-free linear access to memory with increased speed, due to optimized use of hardware resources, including memory, due to use of unified (single) switching circuit values from memory for basic computing units operation "butterfly" for all stages of conveyor.
1 cl, 8 dwg
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Authors
Dates
2020-08-19—Published
2020-01-17—Filed