FIELD: computer technologies.
SUBSTANCE: invention relates to computer technology. A frequency divider with a variable division coefficient contains an element OR with “x” inputs, a synchronization input, “x” logic elements L with the function AND, the first inputs of which are connected to “x” bits of the control bus in reverse order, and the outputs of the elements L are connected to the corresponding inputs of the element OR, the output of which is the information output of the frequency divider, and the first line of “x” single-stage D-triggers with direct dynamic clock inputs are introduced into it, the second line of “x” single-stage D-triggers with inverse static inputs set to “1” and with direct dynamic clock inputs, which these triggers have combined and connected to the synchronization input, as well as to the dynamic clock input of the first trigger of the first line, the direct output of which is connected to the second input of the first logic element L and to the D-input of the first trigger of the second line.
EFFECT: reduction in the conversion time during signal processing.
1 cl, 4 dwg
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Authors
Dates
2021-07-28—Published
2020-12-03—Filed