FIELD: computer engineering. SUBSTANCE: device has address decoder, bus shaper, five AND gates, two OR gates, AND gate group having three states at its output, NAND gate group having three states at its output, memory, two flip-flops, counter, pulse generator, AND gates, OR gate, register, flip-flops, delay gate, group multiplexer, OR gate group, AND gate group, group of majority gates, group of majority gates having inverse outputs, group of three-state majority gates, address inputs, data inputs-outputs, control inputs, resetting input, information inputs, permitting input. EFFECT: increased speed of redundant equipment servicing and order-state testing due to introduced order of preliminary logical processing of three-state signals from detectors and generation of control output vector. 2 dwg
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Authors
Dates
1994-02-15—Published
1990-12-17—Filed