FIELD: microelectronics. SUBSTANCE: device has process 1, clock oscillator 2, system controller 3, address buffer 4, address decoder 5, read-only memory unit 6, main memory unit 7, memory line generator 8, peripheral devices address decoder 9, peripheral devices line generators 10.1-10.l, OR gates 11, 12, input array line generator 13, status code register 14, group of implicit and explicit logical conditions flip-flops 15.1, ..., 15.n, OR gate 16, program address line generator 17, register 18, reset input 19, ready input 20, lock input 21, interrupt request input 22, waiting input 23, permission input 24, group of inputs 25.1-25.l, group of outputs 26.1-26.l, group of explicit logical conditions inputs 27, group of outputs 28 for testing input array, testing outputs 29, 30, program address output 31. EFFECT: increased functional capabilities. 4 dwg, 6 tbl
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Authors
Dates
1997-01-27—Published
1993-04-06—Filed