FIELD: automatics; computer technology. SUBSTANCE: unit has n input and output units of interunit couplings, routing cell, code comparison circuit, the first group of n+1 AND gates, the second group of n AND gates, the third group of n+1 AND gates, group of n+1 NOT gates, the first to the seventh OR gates, the first to the sixth AND gates, the first and the second NOT gates, load flip-flop, assignment flip-flop, delay element, AND-NOT gate, the second group of n AND gates, the third group of n+1 AND gates. Routing cell has AND-NOT gate, the first and the second NOT gates, the first to the sixth AND gates, the first to the fifth OR gates, the first group of n AND gates, the second group of n+1 AND gates, the third group of n+1 AND gates, the third group of n AND gates, group of N OR gates, comparison circuit, OR-NOT gate, readiness flip-flop, resource flip-flop, delay element, n+1 input units. Each input unit has three AND-NOT gates and NOT gate. EFFECT: improved precision. 2 dwg
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Authors
Dates
1994-08-30—Published
1991-06-07—Filed