FIELD: computer technology. SUBSTANCE: code enters shift register of receiving unit in control mode from output of shift register of transmitting unit. After transmission of byte is finished, the contents of shift register of receiving unit is compared with contents of addressed register, where the same code is loaded in control mode, as is loaded in buffer register of transmission. Moreover, comparison signal is used for setting trigger, which is rejected when receiving signal of finish of byte transmission. Potential signal is applied to the bus to be addressed from output of the flip-flop. The bus is available for reading-out address-data devices. Device has interface unit, clock synchronization unit, control unit, address-data bus, receiving unit, transmitting unit and unit for forming interruption signals connected by corresponding couplings. Former, control unit, switch and indication element are brought additionally, as well as corresponding couplings for connecting units. The device may be used as a part of control station of radio-telecontrol system-telesignalling system, which uses mode of synchronous communication to achieve data communication between computer and communication channel. EFFECT: improved truth of inputting data due to program control when data input is done. 2 cl, 8 dwg
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Authors
Dates
1994-09-30—Published
1990-06-11—Filed