FIELD: computer engineering. SUBSTANCE: device having input code converter 1, output code converter 7, and subtracter 6 is provided in addition with constant comparison gate group unit 2, constant multiplying unit 4, OR gate group unit 3, OR gate unit 5, AND gate units 11, 14, comparison unit 12, flip-flop 13. EFFECT: improved speed due to changing working algorithm, separate operations of comparison of numbers and intervals of error distribution. 1 dwg
Title | Year | Author | Number |
---|---|---|---|
DEVICE FOR CHECKING AND CORRECTING ERRORS IN REDUNDANCY MODULAR CODE | 1991 |
|
RU2015620C1 |
DEVICE FOR FAST FOURIER TRANSFORM | 1991 |
|
RU2012051C1 |
ERROR CORRECTION DISCRETE FOURIER TRANSFORM SYSTOLIC PROCESSOR | 1992 |
|
RU2018950C1 |
DEVICE FOR CONVERSION OF NUMBER TO QUADRATIC RESIDUES | 1992 |
|
RU2029436C1 |
NEURON NETWORK FOR FINDING, LOCALIZING AND CORRECTING ERRORS IN RESIDUAL CLASSES SYSTEM | 2005 |
|
RU2301442C2 |
DEVICE FOR HANDLING INFORMATION REPRESENTED IN RESIDUAL CLASS SYSTEM | 0 |
|
SU1743002A1 |
ADAPTIVE PARALLEL-CONVEYOR NEUTRON NETWORK FOR CORRECTION OF ERRORS | 2003 |
|
RU2279131C2 |
DEVICE FOR COMPUTING POSITION CHARACTERISTIC OF POSITION-INDEPENDENT CODE | 1991 |
|
RU2020758C1 |
DEVICE FOR CONVERSION OF NUMBERS FROM CODE OF RESIDUAL CLASS INTO POSITION CODE WITH CHECK OF ERRORS | 0 |
|
SU1797119A1 |
SYSTOLIC PROCESSOR FOR COMPUTING POLYNOMIAL FUNCTIONS | 1991 |
|
RU2015549C1 |
Authors
Dates
1994-10-30—Published
1991-07-10—Filed