FIELD: automatics, computer engineering. SUBSTANCE: combination adder has stages each consisting of three-input one-stage binary adder, majority element, four OR gates, four AND gates, two IMPLICATION elements, inhibition element. Second and third stages have one additional OR gate. EFFECT: increased speed of response of adder thanks to simultaneous summing of three numbers presented in binary excess minimal numbering system. 3 dwg, 1 tbl
| Title | Year | Author | Number |
|---|---|---|---|
| ACCUMULATING ADDER | 1993 |
|
RU2043650C1 |
| ADDER-ACCUMULATOR | 0 |
|
SU1800454A1 |
| COMBINED ADDER | 0 |
|
SU1310808A1 |
| ADDER OF REDUNDANT MINIMUM COMPUTATION SYSTEM | 0 |
|
SU1539768A1 |
| REDUNDANT CODE ADDER | 0 |
|
SU1476460A1 |
| PARALLEL ADDER | 0 |
|
SU1363188A1 |
| REDUNDANT-CODE ACCUMULATOR | 0 |
|
SU1603370A1 |
| COMBINATION ADDER | 0 |
|
SU1442988A1 |
| FIBONACCI CODE ADDER | 0 |
|
SU981993A1 |
| ACCUMULATING ADDER | 0 |
|
SU1532916A1 |
Authors
Dates
1994-11-15—Published
1991-07-01—Filed