ACCUMULATING ADDER Russian patent published in 1995 - IPC

FIELD: automation and computer engineering. SUBSTANCE: device has flip-flop 1 having counting input, AND gates 16-23, 35, OR gates 24-27, delay gates 28-31, modulo-two adder 32, PROHIBITION gates 33, 36, AND gate 34 having direct and inverse inputs. Three delay gates 29-31, two PROHIBITION gates 33, 36, AND gate 35, AND gate 34 having direct and inverse inputs are introduced to accomplish the goal of invention. Device outputs partially reduced sum according to equation given in invention specification. Source numbers are encoded in binary redundant minimal number system. EFFECT: increased speed. 1 dwg