SYSTOLIC FAILURE-PROOF PROCESSOR OF DISCRETE FOURIER TRANSFORM Russian patent published in 1995 - IPC

Abstract RU 2029437 C1

FIELD: computer engineering. SUBSTANCE: systolic failure-proof processor of discrete Fourier transform has two units 4, 6 of conversion of binary code of weight multipliers to systolic failure-proof code, unit 5 of conversion of binary code to systolic failure-proof code, switching-over unit 7, unit 8 of input registers, (n+2) systolic matrixes 9 of Fourier transform by first coordinate with operational units 10, error detector 12, (n+2) adders 13, (n+2) systolic matrixes 14 of Fourier transform by second coordinate with operational units 15, (n+2) units 16 of shift registers with N channels 17 in each unit, unit 18 of conversion of systolic failure-proof code to binary code and synchronization unit 19 connected functionally. EFFECT: increased productivity of processor. 4 cl, 6 dwg

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RU 2 029 437 C1

Authors

Kalmykov Igor' Anatol'Evich

Olenev Aleksandr Anatol'Evich

Dates

1995-02-20Published

1992-06-15Filed