FIELD: automation. SUBSTANCE: output of sixth AND gate is connected to zero-setting input of phase-shift unit. device has pulse counters 1- 3, memory registers 4, 5, correction unit 6, signal delay unit 7, phase shift unit 8, flip-flops 9-13, groups 14-16 of AND gates, AND gates 17-22, delay gates 23-27, code conversion wires 28, control signal wire 29, first wire 30 for reference frequency pulses, time interval wire 31, output wire 32, second wire 33 for reference frequency pulses. Correction unit 6 has two pulse counters, two memory registers, six flip-flops, ten AND gates, three groups of shifting AND gates, delay gate, wire carrying signals from converter counter output having frequency Fco1, wire for reference frequency pulses Fref1, wire for reference frequency pulses Fref2, wire for signals having frequency Fco1, wire for signals having frequency F, OR gate. Signal delay unit 7 has flip-flop register, group of AND gates, group of delay gates, group of OR gates, input signal wire, output wire. Phase shifting unit 8 has flip-flop register, first group of AND gates, second group of AND gates, OR gate, group of delay gates, input signal wire, wire for reference frequency pulses Fref2, output wire and wire for signals from output of first AND gate of code-to-frequency converter. EFFECT: increased precision. 5 dwg
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Authors
Dates
1995-06-19—Published
1992-05-21—Filed