FIELD: radar equipment. SUBSTANCE: detector 1 of signal is connected to first input of logic AND gate 3 and second input of circuit 2 for control over recording which output is linked through recording register 4 to input of interscan storage 5. Output of the latter is connected through reading register 9 to first input of circuit 2 for control over recording linked with third input to output of segment counter 6. Its output is coupled through azimuth adder 8 to output of azimuth counter 7. Output of circuit 2 for control over recording is connected through auxiliary storage 10 and first one-shot multivibrator 11 to second input of logic AND gate 3. Inputs of azimuth 7 and range 12 counters are synchronizing inputs. Output of azimuth counter 7 is linked to input of revolution counter 13 which output is connected to second input of azimuth adder 8. Output of range counter 12 is connected to first input of range adder 14 which second input is linked to output of revolution counter 13. Outputs of azimuth 8 and range 14 adders are connected to inputs of circuit 15 for control over address which output is linked to address input of interscan storage 5. Two channels, one being composed of delay line 16 and second one-shot multivibrator 17 and the other of target counter 18, threshold device 19, register 20 and AND gate 21 which second input is connected to output of one-shot multivibrator 17 and which output is output of interscan device are connected to output of AND gate 3. EFFECT: increased quality of chart-making of nonstationary interference, diminished possibility of false chart-making of single low-speed targets and reduced memory capacity of interscan storage. 1 dwg
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Authors
Dates
1995-07-25—Published
1985-02-22—Filed