MULTIFUNCTIONAL LOGICAL UNIT Russian patent published in 1995 - IPC

FIELD: computer engineering. SUBSTANCE: device has counter, shift register, AND gate, OR gate, comparison unit having inverse input, single-bit adder having multiple inputs, n information inputs, tuning input, reset input, synchronization input and output. Multifunctional logical unit operates as follows. When pulse is sent to reset input, shift register and counter are set to zero. Then vector n(F) is stored to register. Logical one is sent to all information inputs of unit (adder inputs). Binary code that determines number of logical ones containing in input word is generated at output of adder. Unit is tuned to implement symmetric boolean functions F which are encoded in binary code n(F). It speed is nτ/2,, where τ is period of clock pulses. EFFECT: simplified design, increased speed. 1 dwg, 1 tbl