FIELD: pipe line engineering. SUBSTANCE: device has controllable frequency divider the inlet of which is connected to the output of the clock pulse generator (CPG) and output of which is connected to the synchronizing input of the unit for controlling the device (UCD), condition operation switch the output of which is connected with the control input of the controllable divider and 1st UCD, result register the input of which is connected with the outlet of the storage unit of the working memory (WM) and the input of initial setting of the reverse storage counter (RSC) and the output of which is connected with the input of the digital converter, 2nd time delay counter (TDC) the input of the initial setting of which is connected to the output of the TDC setting and the input of the initial setting of the 1st TDC and the output of which is connected with the 2nd inlet of AND element, and switch for setting speed connected with the control input of adjustable generator. The output of the RSC is connected with the input of the SU. The output of gating signal of the control circuit is connected with the synchronizing input of the indicator and the input for permitting initial setting of the 1st TDC. The 1st output of the UCD is connected with the 1st control inlet of the unit for generating an increment. The 2nd control input of the unit is connected with the 2nd output of the UCD. The 3rd output of the unit is connected with the synchronizing input of the control circuit. The input of the initial setting of the circuit is connected with the 1st inputs from the 1st to the 4th unit for controlling memory (UCM), with the input of distance indicator control and 4th output of the UCD. The 5th and 6th output of the control unit are connected with the read enable inputs of the 1st and 2nd buffer units of the WM of the 1st and 2nd pairs respectively. The 7th and 8th outputs of the control unit are connected with the 2nd and 3rd inputs of the 1st and 3rd UCM. The 9th and 10th outputs of the control unit are connected with the 2nd and 3rd inputs of the 2nd and 4th UCM respectively. The read enable input of the SU of the WM is connected with the input of the switching address of the control unit and the 11th output of the UCD. The 12th output of the unit is connected with the 4th inputs of UCM. The 5th inputs of the first two of the units and 5th inputs of the second two of the units are connected to the 13th and 14th inputs of the UCD. The 15th output of the unit is connected with the major digit of the input of the initial setting of the second TDC. The input for permitting initial setting of the counter is connected with the input of the marker push-button, with the control input of the commutator and with the 10th output of the UCD. The 16th and 17th outputs of the unit are connected with the adding and subtracting inputs of the 1st TDC. The 18th outputs of the UCD is connected with the 2nd synchronizing input of the control circuit and with the input for initial setting of the RSC. The reset input of the counter is connected with the 19th output of the UCD. The 20th output of the unit is connected with the subtracting input of the 2nd TDC. The 6th input of the 1st and the 2nd UCM of the 1st and 2nd pairs of the input units of the WM are connected with the 21st and 22nd outputs of the UCD respectively. EFFECT: enhanced accuracy of detecting. 4 cl, 7 dwg
Title | Year | Author | Number |
---|---|---|---|
DEVICE FOR CHECKING QUALITY OF MAGNETIC CARRIER | 1992 |
|
RU2040050C1 |
DEVICE FOR CALCULATION OF CORRELATION FUNCTION | 1992 |
|
RU2037198C1 |
SELECTOR CHANNEL | 0 |
|
SU1103218A1 |
LOGICAL ANALYZER | 0 |
|
SU1432527A1 |
MAJORITY DECODER | 0 |
|
SU1372627A1 |
DEVICE FOR TEST CHECKING OF DIGITAL UNITS | 0 |
|
SU1553978A1 |
DEVICE FOR CHECKING MICROPROCESSOR SYSTEM | 0 |
|
SU1741137A1 |
MULTICHANNEL SYSTEM FOR RECORDING PHYSICAL QUANTITIES | 1991 |
|
RU2037190C1 |
DEVICE FOR COLLECTING INFORMATION OF COMPUTER OPERATION | 0 |
|
SU1121679A1 |
DATA INPUT DEVICE | 0 |
|
SU1145336A1 |
Authors
Dates
1995-10-20—Published
1992-08-07—Filed