FIELD: computer engineering. SUBSTANCE: device has memory unit, processing unit, multiplexer, OR gate, group of AND gates, instruction code register, five flip-flops, two XOR gates, microprogram internal control unit. When device starts, information structure of problem domain is loaded in memory unit. Device receives input task, interprets it according to definition of information structure and outputs result of processing. During interpretation of input task device can output tasks for execution of terminal algorithms and receive logical results of their execution. Device provides possibility to define and interpret recursive, iterative and nested information structures having conjunction, disjunction and inversion operations on predicates. EFFECT: increased functional capabilities, simplified design. 18 dwg
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Authors
Dates
1995-10-20—Published
1991-10-08—Filed