FIELD: computer engineering receivers of time-multiplexing communication channel systems. SUBSTANCE: delay line has input and output amplifiers, two units of series-connected shift registers, storage unit, and clock generator; novelty is that it has, in addition, data write and read sequence automatic monitoring circuit set up of two units monitoring incoming pulses (radio pulses) at input and output of monitoring delay line and two electronic switches controlled by monitoring and controlling units for ON- and OFF-operations of write and read registers. Input monitoring unit sends turn-on pulse to write register switch during rise time of arriving radio pulse and shapes change-over pulse during fall time of this pulse. Change-over pulse is applied to switches of both registers and simultaneously turns off write register and turns on read register. Output monitoring unit sends turn-off pulse to read register switch during fall time of radio pulse arriving at output. Clock generator pulse repetition frequency should be at least twice as maximum frequency of frequency spectrum of information transmitted in radio pulse. Maximum delay time that can be obtained in delay line equals product of number of flip-flops in each shift register by repetition period of clock pulses. EFFECT: improved design; operation in communication channels receiving signals from installations handling pulses (radio pulses) of different lengths. 8 dwg
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Authors
Dates
1997-07-20—Published
1993-08-31—Filed