FIELD: computer engineering, in particular, high-precision instruments for stellar navigation, radar and under-water location. SUBSTANCE: device has three registers 1, 8, 14, two multiplexers 6, 9, constant register 14, decoder, three shift registers 15, 16, 17, three multiplication units 2, 18, 19, two sign-inversion units 20, 21, four adders 3, 7, 10, 22, D flip-flop 4. Output of first adder is connected to output of filter. In addition device has second D flip-flop 11 and OR gate 12. This results in possibility to reset delay registers with intermediate filtration results when arithmetic overflow happens in output adder. Output of second D flip-flop may be used as bit which acknowledges distortion of filtration results as well as for decision making in information systems which use this digital filter. EFFECT: increased functional capabilities. 4 dwg
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Authors
Dates
1997-11-27—Published
1994-09-29—Filed