FIELD: digital communications, automation and computer engineering, in particular, parallel detectors of channel digital signals, alarm equipment and devices which count number of ones in binary combination. SUBSTANCE: goal of invention is achieved by logical addition of partial sums which are result of bit-wise multiplication of input codes, and pair- wise logical multiplication of signals of bit-wise logical addition of input codes. Same bits are subjected to bit-wise operations. This entails that input codes do not enter into sum code. Number of partial sums and AND gates which implement them is decreased down to N(N+1)/2. EFFECT: elimination of superposition of input codes to output sum code, simplified design. 2 dwg
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Authors
Dates
1999-04-27—Published
1997-10-29—Filed