FIELD: modeling phase chatter of digital data signals for checking data synchronizers and decoders. SUBSTANCE: pulse generator has clock generator and pseudorandom number generator; clock generator output is connected to pseudorandom number generator input and to output terminal of device through series circuit set up of identical controlled delay circuits which function to delay pulse in response to control signal and not to delay it in absence of this signal. Control inputs of controlled delay circuits are connected to respective outputs of group of adjacent bits of pseudorandom number generator and their reference inputs, to common adjustable reference voltage terminal. In this way, desired phase noise chattering is maintained within desired frequency spectrum. EFFECT: simplified design , provision for maintaining normalized phase chattering. 3 dwg
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Authors
Dates
1999-07-20—Published
1998-04-24—Filed