FIELD: electrical engineering. SUBSTANCE: sync signal is shifted in phase through value depending on control signal by organizing at least several sampled delay periods required for sync signal. Sampled delay time introduced in sync signal is chosen depending to control signal value. Data signal in the form of bits presenting varying phase and selected phase-shifted sync signal are applied to phase-locked loop of analog-to-digital converter which makes it possible to control signal value. At least several cascade delay lines having actually equal delay time provide for obtaining chosen copy of sync signal. One of versions uses multiplexer which is supplied with sync signal and signal presented in Gray code to control connection of one of delay lines to output. In other version, number of cascade delay lines inserted between sync signal source and output is controlled by signal value. EFFECT: improved design of device. 23 cl, 6 dwg
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Authors
Dates
1999-11-10—Published
1993-12-22—Filed