FIELD: computer engineering; data loading from random-access memory to processor unit. SUBSTANCE: system has processor unit, randomaccess memory, buffer memory, controller unit for swapping data from M controllers; controller unit for data reading from K controllers, address data memory, and area index memory. Asynchronous procedure for loading data arrays using components of mentioned system is given in description of invention. EFFECT: increased capacity; provision for adapting to randomaccess memory delays. 17 cl, 9 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| DEVICE FOR COMMAND SAMPLING | 0 |
|
SU726533A1 |
| BUFFER STORAGE CONTROL DEVICE | 0 |
|
SU737952A1 |
| CENTRAL PROCESSOR | 0 |
|
SU1804645A3 |
| COMMAND SHAPING DEVICE | 0 |
|
SU734686A1 |
| COMPUTING SYSTEM | 0 |
|
SU1777148A1 |
| COMPUTING SYSTEM | 0 |
|
SU692400A1 |
| PARALLEL PROCESSOR WITH SOFT-WIRED STRUCTURE | 1994 |
|
RU2110088C1 |
| BUFFER MEMORY CONTROL UNIT | 1990 |
|
RU2010317C1 |
| MULTIFUNCTIONAL ABOARD INDICATOR | 2000 |
|
RU2162204C1 |
| CONTROL VECTOR COMPUTER SYSTEM | 0 |
|
SU1120340A1 |
Authors
Dates
2001-05-10—Published
2000-07-20—Filed