DEVICE FOR ESTIMATING DEGREE OF LAYOUT OPTIMIZATION Russian patent published in 2001 - IPC

Abstract RU 2177172 C1

FIELD: computer engineering; modeling combinatorial problems in components layout design. SUBSTANCE: device has matrix of m lines and n columns of homogeneous-medium components, maximum detecting units, adder, memory unit, ones counting units, channel loading evaluation unit, column selection decoder, AND, OR gates, channel loading counters, column counter, inhibit gate, delay element, pulse generator, and channel loading register. EFFECT: enlarged functional capabilities due to including channel loading criterion between adjacent components. 5 dwg

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RU 2 177 172 C1

Authors

Borzov D.B.

Zotov I.V.

Titov V.S.

Dates

2001-12-20—Published

2000-05-25—Filed